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final publication# 19521 rev: d amendment/ 0 issue date: december 1996 amc0xxdflka 4, 8, 20, or 32 megabyte 5.0 volt-only flash memory pc card distinctive characteristics n high performance 150 ns maximum access time n single supply operation write and erase voltage, 5.0 v 5% read voltage, 5.0 v 5% n cmos low power consumption 45 ma maximum active read current (x8 mode) 65 ma maximum active write/erase current (x8 mode) n high write endurance minimum 100,000 program/erase cycles per sector 1,000,000 typical program/erase cycles per card n pcmcia/jeida 68-pin standard selectable byte-/or word-wide con?uration n write protect switch prevents accidental data loss n zero data retention power batteries not required for data storage n enhanced power management for standby mode ? m a typical standby current standard access time from standby mode n separate attribute memory n automated write and erase operations increase system write performance 64k byte memory sectors for faster automated erase speed typically 1 s per single memory sector erase random address writes to previously erased bytes (8 m s typical per byte) n total system integration solution support from independent software and hardware vendors n low insertion and removal force state-of-the-art connector allows for minimum card insertion and removal effort n erase suspend/resume supports reading or programming data to a sector not being erased within the same device n support for ry/by and reset signals general description amds 5.0 volt-only flash memory pc card provides the highest system level performance for data and ?e storage solutions to the portable pc market segment and a wide range of embedded applications. manufac- tured with amds negative gate erase, 5.0 volt-only technology, the amd 5.0 volt-only flash memory cards are the most cost-effective and reliable ap- proach to single-supply flash memory cards. data ?es and application programs can be stored on the d-se- ries cards. this allows oem manufacturers of portable systems to eliminate the weight, high-power consump- tion and reliability issues associated with electro-mechanical disk-based systems. the d-series cards also allow todays bulky and heavy battery packs to be reduced in weight and size. amds flash memory pc cards provide the most ef?ient method to transfer useful work between different hardware platforms. the enabling technology of the d-series cards enhances the productivity of mobile workers. widespread acceptance of the d-series cards is assured due to their compatibility with the 68-pin pcmcia/jeida international standard. amds flash memory cards can be read in either a byte-wide or word-wide mode which allows for ?xible integration into various system platforms. compatibility is assured at the hardware interface and software interchange speci?ation. the card information structure (cis) or metaformat, can be written by the oem into the mem- ory cards attribute memory address space beginning at address 00000h by using a format utility. the cis appears at the beginning of the cards attribute mem- ory space and de?es the low-level organization of data on the pc card. the d-series cards contains a separate eeprom memory for the cards attribute memory space. this allows all of the flash memory to be used for the common memory space. third party software solutions such as microsoft? and systemsoft? flash file system (ffs2), scm? scm-ftl, and datalight? cardtrick enable amd? flash memory pc card to replicate the function of traditional disk-based memory systems.
2 amc0xxdflka block diagram notes: r = 20 k(min)/140 k w (max) *4 mbyte card = s0 + s1, 8 mbyte card = s0?3, 20 mbyte card = s0?9, 32 mbyte card = s0?15 address buffers and decoders i/o transceivers and buffers a0?8 d0?7 attribute memory ce write protect switch v cc d0?15 we oe d8?15 d0?7 a0 a1?24 ce 2 ce 1 a1?9 a0 ce 2 ce 1 reg cd 1 cd 2 card detect gnd v cc r r decoder v cc rr am29f016c a0?20 d0?7 ce we oe ry/by v ss v cc rst s0* am29f016c a0?20 d8?15 ce we oe ry/by v ss v cc rst s1* a0?20 d0?7 ce we oe ry/by v ss v cc rst s2* a0?20 d8?15 ce we oe ry/by v ss v cc rst s3* a0?20 d0?7 ce we oe ry/by v ss v cc rst s14* a0?20 d8?15 ce we oe ry/by v ss v cc rst s15* 19521d-1 wp 10k 10k a0?24 ice7 ice0 ice1 ioel iwel ioeh iweh a1-a21 v cc reset ry/by (output) r v cc 3.3k
amc0xxdflka 3 pc card pin assignments notes: i = input to card, o = output from card i/o = bidirectional nc = no connect in systems which switch v cc individually to cards, no signal should be directly connected between cards other than ground. 1. v pp not required for programming or reading operations. 2. bvd = internally pulled-up. 3. signal must not be connected between cards. pin# signal i/o function pin# signal i/o function 1 gnd ground 35 gnd ground 2 d3 i/o data bit 3 36 cd 1 o card detect 1 (note 3) 3 d4 i/o data bit 4 37 d11 i/o data bit 11 4 d5 i/o data bit 5 38 d12 i/o data bit 12 5 d6 i/o data bit 6 39 d13 i/o data bit 13 6 d7 i/o data bit 7 40 d14 i/o data bit 14 7ce 1 i card enable 1 (note 3) 41 d15 i/o data bit 15 8 a10 i address bit 10 42 ce 2 i card enable 2 (note 3) 9oe i output enable 43 nc no connect 10 a11 i address bit 11 44 nc no connect 11 a9 i address bit 9 45 nc no connect 12 a8 i address bit 8 46 a17 i address bit 17 13 a13 i address bit 13 47 a18 i address bit 18 14 a14 i address bit 14 48 a19 i address bit 19 15 we i write enable 49 a20 i address bit 20 16 ry/by ready/busy 50 a21 i address bit 21 17 v cc1 power supply 51 v cc2 power supply 18 nc no connect (note 1) 52 nc no connect (note 1) 19 a16 i address bit 16 53 a22 i address bit 22 20 a15 i address bit 15 54 a23 i address bit 23 21 a12 i address bit 12 55 a24 i address bit 24 22 a7 i address bit 7 56 nc no connect 23 a6 i address bit 6 57 nc no connect 24 a5 i address bit 5 58 reset reset 25 a4 i address bit 4 59 nc no connect 26 a3 i address bit 3 60 nc no connect 27 a2 i address bit 2 61 reg i register select 28 a1 i address bit 1 62 bvd 2 o battery vltg detect 2 (note 2) 29 a0 i address bit 0 63 bvd 1 o battery vltg detect 1 (note 2) 30 d0 i/o data bit 0 64 d8 i/o data bit 8 31 d1 i/o data bit 1 65 d9 i/o data bit 9 32 d2 i/o data bit 2 66 d10 i/o data bit 10 33 wp o write protect (note 3) 67 cd 2 o card detect 2 (note 3) 34 gnd ground 68 gnd ground
4 amc0xxdflka ordering information standard products amd standard products are available in several packages and operating ranges. the order number (valid combination) is formed by a combination of: output configuration: (x16/x8) flash technology pc memory card memory card density 004 = four megabytes 008 = eight megabytes 020 = twenty megabytes 032 = thirty-two megabytes amd revision level 5.0 volt-only operation with 100,000 erase/program cycles minimum am c 0xx d fl k a csxxxxx customer specific identification number
amc0xxdflka 5 differences between the d-series and c-series cards the differences between the d-series card and the earlier c-series cards are as follows: n the d-series cards are based on amds latest 16 mbit 5.0 volt-only device, the am29f016c. the ear- lier c-series cards were based on the 4 mbit 5.0 volt-only device, the am29f040. n the d-series cards program faster than the c- series cards. this is due to faster byte write times and an optimized address unlock sequence for write operations. n the d-series cards are offered in higher densi- ties. the d-series cards are available in densities of 4 mbytes, 8 mbytes, 20 mbytes, and 32 mbytes. the earlier c-series cards were avail- able in densities of 1 mbyte, 2 mbytes, 4 mbytes and 10 mbytes. the additional features that are supported in the new d-series cards include n the d-series cards support the reset feature. this allows you to asynchronously reset the card into the read state. n the d-series cards also provide the ry/by func- tionality. this feature provides a quick way of deter- mining if the card is busy doing a write or erase operation, or if it is in a position to undertake the next operation. n availability of an additional toggle bit (d2) to deter- mine if the card is in the embedded erase or erase suspend mode. n programming operations can be executed in 8 m s pulses, down from the 16 m s on the c-series cards (typical). n time out from the rising edge of the we pulse for sector erase command reduced from 100 m s to 50 m s. n the d-series cards offers a low power standby mode with fast recovery time to read. the typical standby current (i ccs ) is <1 m a with recovery at standard read access time.
6 amc0xxdflka pin description a0?24 address inputs these inputs are internally latched during write cycles. all address lines should be driven. bvd 1, bvd 2 battery voltage detect internally pulled-up. cd 1, cd 2 card detect when card detect 1 and 2 = ground the system detects the card. ce 1, ce 2 card enable this input is active low. the memory card is deselected and power consumption is reduced to standby levels when ce is high. ce activates the internal memory card circuitry that controls the high and low byte control logic of the card, input buffers segment decoders, and associated memory devices. d0?15 data input/output data inputs are internally latched on write cycles. data outputs during read cycles. data pins are active high. when the memory card is deselected or the outputs are disabled the outputs ?at to tristate. gnd ground nc no connect corresponding pin is not connected. oe output enable this input is active low and enables the data buffers through the card outputs during read cycles. ry/by this signal is output from the card and indicates the status of the operation in progress in the card. if this signal is low, then the card is still busy with the current operation. otherwise, the card is ready to accept anew operation. reg attribute memory select this input is active low and enables reading the cis from the eeprom. reset this input to the card is used to reset all the flash de- vices inside the card to a read mode state. if you drive or assert reset high during a write or erase opera- tion, then the state of the devices for the purpose of the operation is undefined. in order to reset, you need to hold the reset pin high for 500 ns, and it takes 20 m s before the internal circuit is reset. when reset is driven high, the data bus is in a high impedance state. v cc pc card power supply for device operation (5.0 v 5%). we write enable this input is active low and controls the write function of the command register to the memory array. the target address is latched on the falling edge of the we pulse and the appropriate data is latched on the rising edge of the pulse. wp write protect this output is active high and disables all card write operations (including writes to the attribute memory). memory card operations the d-series flash memory card is organized as an array of individual devices. each device is 2 mbytes in size with thirty-two 64k byte sectors. although the ad- dress space is continuous, each physical device de- fines a logical address segment size. erase operations can be performed on two 64kbyte sectors simultaneously. once a memory sector or memory segment is erased any address location may be programmed. flash technology allows any logical ??data bit to be programmed to a logical ?? the only way to reset bits to a logical ??is to erase the entire memory sector of 64k bytes or memory seg- ment of 2 mbytes. erase operations are the only operations that work on entire memory sectors or memory segments. all other operations such as word-wide programming are not af- fected by the physical memory segments. the common memory space data contents are altered in a similar manner as writing to individual flash mem- ory devices. on-card address and data buffers activate the appropriate flash device in the memory array. each device internally latches address and data during write cycles. refer to table 1. attribute memory is a separately accessed card mem- ory space. the attribute memory space is active when the reg pin is driven low. the card information struc- ture (cis) describes the capabilities and specification
amc0xxdflka 7 of a card. the cis is stored in the attribute memory space beginning at address 00000h. the d-series cards contain a separate eeprom for the card infor- mation structure. d0?7 are active during attribute memory accesses. d8?15 should be ignored. odd or- der bytes present invalid data. refer to table 2. word-wide operations the d-series cards provide the flexibility to operate on data in a byte-wide or word-wide format. in word-wide operations the ce 1 and ce 2 must be low and a0 is not used for any addressing. table 1. common memory bus operations notes: 1. x indicates a don? care value. 2. v pp pins are not connected in the 5.0 volt-only flash memory card. 3. refer to table 5 for valid d in during a word write operation. 4. refer to table 3 and 4 for valid d in during a byte write operation. 5. during odd byte access, a0 = v ih outputs or inputs the ?dd byte (high byte) of the x16 word on d0?7. this is accomplished internal to the card by transposing d8?15 to d0?7. 6. during odd-byte-only access , a0 = x outputs or inputs the ?dd byte (high byte) of the x16 word on d8?15. function reg ce 2ce 1oe we a0 d8?15 d0?7 read mode standby mode x h h x x x high-z high-z word access h l l l h x data out-odd data out-even low byte access h h l l h l high-z data out-even odd byte access h h l l h h high-z data out-odd odd-byte-only access hlhlhx data out-odd high-z write mode standby mode x h h x x x x x word access (note 3) h l l h l x data in-odd data in-even even byte access (note 4) h hlhll high-z data in-even odd byte access (note 4) h hlhlh high-z data in-odd odd-byte-only access (note 4) h l h h l x data in-odd high-z output disable h x x h h x high-z high-z
8 amc0xxdflka table 2. attribute memory bus operations notes: 1. x indicates any value. 2. v pp pins are not connected in the 5.0 volt-only flash memory card. 3. during attribute memory read function, reg and oe must be active for the entire cycle. 4. only even-byte data is valid during attribute memory read function. 5. during attribute memory write function, reg and we must be active for the entire cycle, oe must be inactive for the entire cycle. 6. the ?st 128 bytes of the attribute memory is not writable as it contains the cis. only the remaining 384 bytes are writable. pins/operation reg ce 2ce 1oe we a0 d8?15 d0?7 read/write read mode (note 3) standby mode x h h x x x high-z high-z word access (note 4) llllhx not valid data out-even even byte access l h l l h l high-z data out-even odd byte access (note 4) l h l l h h high-z not valid odd-byte-only access (note 4) l lhlhx not valid high-z write mode (note 5,6) standby mode x h h x x x x x word access l l l h l x x data in-even low byte access lhlhll x data in-even odd byte access lhlhlh x x odd-byte-only access l l h x h l x x output disable l x x h h x high-z high-z
amc0xxdflka 9 byte-wide operations byte-wide data is available on d0?7 for read and write operations (ce 1 = low, ce 2 = high). even and odd bytes are stored in separate memory segments (i.e., s0 and s1) and are accessed when a0 is low and high respectively. the even byte is the low order byte and the odd byte is the high order byte of a 16-bit word. erase operations in the byte-wide mode must account for data multiplexing on d0?7 by changing the state of a0. each memory sector or memory segment pair must be addressed separately for erase operations. card detection each cd (output) pin should be read by the host sys- tem to determine if the memory card is adequately seated in the socket. cd 1 and cd 2 are internally tied to ground. if both bits are not detected, the system should indicate that the card must be reinserted. write protection the amd flash memory card has three types of write protection. the pcmcia/jeida socket itself provides the ?st type of write protection. power supply and con- trol pins have speci? pin lengths in order to protect the card with proper power supply sequencing in the case of hot insertion and removal. a mechanical write protect switch provides a second type of write protection. when this switch is activated, we is internally forced high. the flash memory com- mand register is disabled from accepting any write commands. the third type of write protection is achieved with v cc1 and v cc2 below 3.2 v v lko . each flash memory de- vice that comprises a flash memory segment will reset the command register to the read-only mode when v cc is below v lko . v lko is the voltage below which write operations to individual command regis- ters are disabled. memory card bus operations read enable two card enable (ce ) pins are available on the mem- ory card. both ce pins must be active low for word-wide read accesses. only one ce is required for byte-wide accesses. the ce pins control the selection and gates power to the high and low memory seg- ments. the output enable (oe ) controls gating ac- cessed data from the memory segment outputs. the device will automatically power-up in the read/ reset state. in this case, a command sequence is not required to read data. standard microprocessor read cycles will retrieve array data. this default value en- sures that no spurious alteration of the memory content occurs during the power transition. refer to the ac read characteristics and waveforms for the speci? timing parameters. output disable data outputs from the card are disabled when oe is at a logic-high level. under this condition, outputs are in the high-impedance state. standby operations byte-wide read accesses only require half of the read/ write output buffer (x16) to be active. in addition, only one memory segment is active within either the high order or low order bank. activation of the appropriate half of the output buffer is controlled by the combination of both ce pins. the ce pins also control power to the high and low-order banks of memory. outputs of the memory bank not selected are placed in the high im- pedance state. the individual memory segment is acti- vated by the address decoders. the other memory segments operate in standby. an active memory seg- ment continues to draw power until completion of a write or erase operation if the card is deselected in the process of one of these operations. auto select operation a host system or external card reader/writer can deter- mine the on-card manufacturer and device i.d. codes. codes are available after writing the 90h command to the command register of a memory segment per tables 3 and 4. reading from address location 00000h in any segment provides the manufacturer i.d. while address location 00002h provides the device i.d. to terminate the auto select operation, it is neces- sary to write the read/reset command sequence into the register. write operations write and erase operations are valid only when v cc1 and v cc2 are above 4.75 v. this activates the state ma- chine of an addressed memory segment. the com- mand register is a latch which saves address, commands, and data information used by the state ma- chine and memory array. when write enable (we ) and appropriate ce (s) are at a logic-level low, and output enable (oe ) is at a logic-high, the command register is enabled for write operations. the falling edge of we latches address in- formation and the rising edge latches data/command information. write or erase operations are performed by writing ap- propriate data patterns to the command register of ac- cessed flash memory sectors or memory segments. the byte-wide and word-wide commands are de?ed in tables 3, 4, and 5, respectively.
10 amc0xxdflka table 3. even byte command de?itions (note 5) * address for memory segment 0 (s0) only. address for the higher even memory segments (s2?14) = (addr) + (n/2)* 400000h where n = memory segment number (0) for 4 mbyte, n = (0, 2) for 8 mbyte, n = (0, 2, 4) for 12 mbyte, n = (0?) for 20 mbyte, n = (0...14) for 32 mbyte. notes: 1. address bits = x = don? care for all address commands except for program address (pa), read address (ra) and sector address (sa). 2. bus operations are de?ed in table 1. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a17, a18, a19, a20, a21 will uniquely select any sector of a segment. to select the memory segment: 4 mbyte: use ce 1 8 mbyte: use ce 1 and a22 20 and 32 mbyte: use ce 1 and a22-a24. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we pulse. 5. a0 = 0 and ce 1 = 0. embedded command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr* data addr* data addr* data addr* data addr* data addr* data reset/read 1 xxxxh f0 reset/read 4 xxxxh aa xxxxh 55 xxxxh f0 ra rd autoselect 4 xxxxh aa xxxxh 55 xxxxh 90 00h 01 02h 3d byte write 4 xxxxh aa xxxxh 55 xxxxh a0 pa pd segment erase 6 xxxxh aa xxxxh 55 xxxxh 80 xxxxh aa xxxxh 55 xxxxh 10 sector erase 6 xxxxh aa xxxxh 55 xxxxh 80 xxxxh aa xxxxh 55 sa 30 sector erase suspend xxxxh b0 erase can be suspended during sector erase with addr (don? care), data (b0h) sector erase resume xxxxh 30 erase can be resumed after suspend with addr (don? care), data (30h)
amc0xxdflka 11 table 4. odd byte command de?itions (notes 1?) * address for memory segment 1 (s1) only. address for the higher odd memory segments (s3?15) = (addr) + ((n?)/2)* 400000h + 20000h where n = memory segment number (1) for 4 mbyte, n = (1, 3) for 8 mbyte, n = (1, 3, 5) for 12 mbyte, n = (1?) for 20 mbyte, n = (1...15) for 32 mbyte. notes: 1. address bits = x = don? care for all address commands except for program address (pa), read address (ra) and sector address (sa). 2. bus operations are de?ed in table 1. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a17, a18, a19, a20, a21 will uniquely select any sector of a segment. to select the memory segment: 4 mbyte: use ce 2 8 mbyte: use ce 2 and a22 20 and 32 mbyte: use ce 2 and a22?24. 4. rd = data read from location ra during read operation. pd = data to be programmed at location pa. data is latched on the rising edge of we pulse. 5. a0 = 1 and ce 1 = 0 or a0 = x and ce 2 = 0. embedded command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr* data addr* data addr* data addr* data addr* data addr* data reset/read 1 xxxxh f0 reset/read 4 xxxxh aa xxxxh 55 xxxxh f0 ra rd autoselect 4 xxxxh aa xxxxh 55 xxxxh 90 00h 01 02h 3d byte write 4 xxxxh aa xxxxh 55 xxxxh a0 pa pd segment erase 6 xxxxh aa xxxxh 55 xxxxh 80 xxxxh aa xxxxh 55 xxxxh 10 sector erase 6 xxxxh aa xxxxh 55 xxxxh 80 xxxxh aa xxxxh 55 sa 30 sector erase suspend xxxxh aa erase can be suspended during sector erase with addr (don? care), data (b0h) sector erase resume xxxxh aa erase can be resumed after suspend with addr (don? care), data (30h)
12 amc0xxdflka table 5. word command de?itions (notes 1?) notes: 1. address bits = x = don? care for all address commands except for program address (pa) and sector address (sa). 2. bus operations are de?ed in table 1. 3. ra = address of the memory location to be read. pa = address of the memory location to be programmed. addresses are latched on the falling edge of the we pulse. sa = address of the sector to be erased. the combination of a17, a18, a19, a20, a21will uniquely select any sector of a segment. to select the memory segment: 4 mbyte: use ce 1, ce 2 8 mbyte: use ce 1, ce 2 20 and 32 mbyte: use ce 1, ce 2, a22?24. 4. rw = data read from location ra during read operation. (word mode). pw = data to be programmed at location pa. data is latched on the rising edge of we . (word mode). 5. address for memory segment pair 0 (s0 and s1) only. address for the higher memory segment pairs (s2, s3 = pair 1; s4, s5 = pair 2; s6, s7 = pair 3? is equal to (addr) + m* (40000h) where m = memory segment pair number. 6. word = 2 bytes = odd byte and even byte. 7. ce 1 = 0 and ce 2 = 0. embedded command sequence bus write cycles reqd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr* data addr* data addr* data addr* data addr* data addr* data reset/read 1 xxxxh f0f0 reset/read 4 xxxxh aaaa xxxxh 5555 xxxxh f0 ra rw autoselect 4 xxxxh aaaa xxxxh 5555 xxxxh 90 00h 0101 02h 3d3d byte write 4 xxxxh aaaa xxxxh 5555 xxxxh a0a0 pa pw segment erase 6 xxxxh aaaa xxxxh 5555 xxxxh 8080 xxxxh aaaa 5554h 5555 xxxxh 1010 sector erase 6 xxxxh aaaa xxxxh 5555 xxxxh 8080 xxxxh aaaa 5554h 5555 sa 3030 sector erase suspend xxxxh b0b0 erase can be suspended during sector erase with addr (don? care), data (b0b0h) sector erase resume xxxxh 3030 erase can be resumed after suspend with addr (don? care), data (3030h)
amc0xxdflka 13 flash memory program/erase operations details of amds embedded write and erase operations embedded erase algorithm the automatic memory sector or memory segment erase does not require the device to be entirely pre-programmed prior to executing the embedded erase command. upon executing the embedded erase command sequence, the addressed memory sector or memory segment will automatically write and verify the entire memory segment or memory sector for an all ?ero data pattern. the system is not required to pro- vide any controls or timing during these operations. when the memory sector or memory segment is au- tomatically veri?d to contain an all ?ero pattern, a self-timed chip erase-and-verify begins. the erase and verify operations are complete when the data on d7 (d15 on the odd byte) of the memory sector or memory segment is ? (see write operation status section) at which time the device returns to the read mode. the system is not required to provide any con- trol or timing during these operations. a reset com- mand after the device has begun execution will stop the device but the data in the operated segment will be unde?ed. in that case, restart the erase on that sector and allow it to complete. when using the embedded erase algorithm, the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase ver- ify command is required). the margin voltages are in- ternally generated in the same manner as when the standard erase verify command is used. the embedded erase command sequence is a com- mand only operation that stages the memory sector or memory segment for automatic electrical erasure of all bytes in the array. the automatic erase begins on the rising edge of the we and terminates when the data on d7 of the memory sector or memory segment is ? (see write operation status section) at which time the device returns to the read mode. please note that for the memory segment or memory sector erase opera- tion, data polling may be performed at any address in that segment or sector. figure 1 and table 6 illustrate the embedded erase al- gorithm, a typical command string and bus operations. as described earlier, once the memory sector in a de- vice or memory segment completes the embedded erase operation it returns to the read mode and ad- dresses are no longer latched. therefore, the device requires that the address of the sector being erased is supplied by the system at this particular instant of time. otherwise, the system will never read a ? on d7. a system designer has two choices to implement the em- bedded erase algorithm: 1. the system (cpu) keeps the sector address (within any of the sectors being erased) valid during the en- tire embedded erase operation, or 2. once the system executes the embedded erase command sequence, the cpu takes away the ad- dress from the device and becomes free to do other tasks. in this case, the cpu is required to keep track of the valid sector address by loading it into a tem- porary register. when the cpu comes back for per- forming data polling, it should reassert the same address. since the embedded erase operation takes a signi? cant amount of time (1 s?0 s), option 2 makes more sense. however, the choice of these two options has been left to the system designer. figure 1 and table 6 illustrate the embedded erase al- gorithm, a typical command string and bus operations. sector erase sector erase is a six bus cycle operation. there are two ?nlock write cycles. these are followed by writ- ing the ?et up command. two more ?nlock write cy- cles are then followed by the sector erase command. the sector address (any address location within the desired sector) is latched on the falling edge of we , while the command (data) is latched on the rising edge of we . a time-out of 50 m s from the rising edge of the last sector erase command will initiate the sec- tor erase command(s). multiple sectors may be erased by writing the six bus cycle operations as described above. this sequence is followed with writes of the sector erase command 30h to addresses in other sectors to be erased. a time-out of 50 m s from the rising edge of the we pulse for the last sector erase command will initiate the sector erase. if another sector erase command is written within the 50 m s time-out window the timer is reset. any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previ- ous command string (refer to write operation status section for sector erase timer operation). loading the sector erase buffer may be done in any sequence and with anysector number. table 6. embedded erase algorithm bus operation command comments standby wait for v cc ramp write embedded erase command sequence 6 bus cycle operation read data polling to verify erasure
14 amc0xxdflka sector erase does not require the user to program the device prior to erase. the device automatically pro- grams all memory locations to ? in the sector(s) to be erased prior to electrical erase. when erasing a sector or sectors the remaining unselected sectors are not af- fected. the system is not required to provide any con- trols or timings during these operations. a reset command after the device has begun execution will stop the device but the data in the operated sector will be undened. in that case, restart the erase on that sector and allow it to complete. the automatic sector erase begins after the 50 m s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on d7 is ? (see write operation status section) at which time the device returns to read mode. data polling must be performed at an address within any of the sectors being erased. figure 1 illustrates the embedded erase algorithm using typical command strings and bus operations. embedded program algorithm the embedded program setup is a four bus cycle op- eration that stages the addressed memory sector or memory segment for automatic programming. once the embedded program setup operation is per- formed, the next we pulse causes a transition to an ac- tive programming operation. addresses are internally latched on the falling edge of the we pulse. data is in- ternally latched on the rising edge of the we pulse. the rising edge of we also begins the programming opera- tion. the system is not required to provide further con- trol or timing. the device will automatically provide an adequate internally generated write pulse and verify margin. the automatic programming operation is com- pleted when the data on d7 of the addressed memory sector or memory segment is equivalent to data written to this bit (see write operation status section) at which time the device returns to the read mode (no write ver- ify command is required). addresses are latched on the falling edge of we during the embedded program command execution and hence the system is not required to keep the addresses stable during the entire programming operation. how- ever, once the device completes the embedded pro- gram operation, it returns to the read mode and addresses are no longer latched. therefore, the device requires that a valid address input to the device is sup- plied by the system at this particular instant of time. otherwise, the system will never read a valid data on d7. a system designer has two choices to implement the embedded programming algorithm: 1. the system (cpu) keeps the address valid during the entire embedded programming operation, or 2. once the system executes the embedded program- ming command sequence, the cpu takes away the address from the device and becomes free to do other tasks. in this case, the cpu is required to keep track of the valid address by loading it into a temporary register. when the cpu comes back for performing data polling, it should reassert the same address. however, since the embedded programming operation takes only 8 m s typically, it may be easier for the cpu to keep the address stable during the entire embedded programming operation instead of reasserting the valid address during data polling. anyway, this has been left to the system designers choice to go for either opera- tion. any commands written to the segment during this period will be ignored. figure 2 and table 7 illustrate the embedded program algorithm, a typical command string, and bus operation. reset command the reset command initializes the sector or segment to the read mode. please refer to tables 3 and 4, ?yte command de?itions, and table 5, ?ord command denitions for the reset command operation. the sector or segment remains enabled for reads until the command register contents are altered. 19521d-2 figure 1. embedded erase algorithm write embedded erase command sequence (table 3 and 4) data poll from device (figure 3) start erasure complete table 7. embedded program algorithm bus operation command comments standby wait for v cc ramp write embedded program command sequence 3 bus cycle operation write program address/ data 1 bus cycle operation read data polling to verify program
amc0xxdflka 15 the reset command will safely reset the segment memory to the read mode. memory contents are not altered. following any other command, write the reset command once to the segment. this will safely abort any operation and reset the device to the read mode. the reset is needed to terminate the auto select oper- ation. it can be used to terminate an erase or sector erase operation, but the data in the sector or segment being erased would then be unde?ed. write operation status ry/by ready/busy the d-series card provides a ry/by output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been com- pleted. if the output is low, the card is busy with either a program or erase operation. if the output is high, the card is ready to accept any read/write or erase opera- tion. when the ry/by pin is low, the card will not accept any additional program or erase commands with the exception of the erase suspend command to the same device pair, one can still write or erase to a different de- vice pair. if the card is placed in an erase suspend mode, the ry/by output will be high. during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. refer to fig- ure 21 for a detailed timing diagram. the ry/by pin is pulled high in standby mode. ry/by is best used to in- terrupt the cpu when an erase completes. polling is best for byte programming. data polling?7 (d15 on odd byte) the flash memory pc card features data polling as a method to indicate to the host system that the embed- ded algorithms are either in progress or completed. while the embedded programming algorithm is in op- eration, an attempt to read the device will produce the complement of expected valid data on d7 of the ad- dressed memory sector or memory segment. upon completion of the embedded program algorithm an at- tempt to read the device will produce valid data on d7. the data polling feature is valid after the rising edge of the fourth we pulse of the four write pulse sequence. while the embedded erase algorithm is in operation, d7 will read ? until the erase operation is completed. upon completion of the erase operation, the data on d7 will read ?? the data polling feature is only active during the em- bedded programming or erase algorithms. please note that the amc0xxdflka data pin (d7) may change asynchronously while output enable (oe ) is asserted low. this means that the device is driving status infor- mation on d7 at one instant of time and then the bytes valid data at the next instant of time. depending on 19521d-3 figure 2. embedded programming algorithm in byte-wide mode write embedded write command sequence per table 3 or 4 verify byte no ye s data poll device ye s increment address no start completed last address
16 amc0xxdflka when the system samples the d7 output, it may read either the status or valid data. even if the device has completed the embedded operation and d7 has a valid data, the data outputs on d0?6 may be still in- valid since the switching time for data bits (d0?7) will not be the same. this happens since the internal delay paths for data bits (d0?7) within the device are differ- ent. the valid data will be provided only after a certain time delay ( amc0xxdflka 17 two status bits, along with that of d7, is summarized as follows: notes: 1. these status ?gs apply when outputs are read from a sector that has been erase-suspended. 2. these status ?gs apply when outputs are read from the byte address of the non-erase suspended sector. sector erase suspend sector erase suspend command allows the user to in- terrupt the chip and then do data reads (or program) from a non-busy sector while it is in the middle of a sec- tor erase operation (which may take up to several sec- onds). this command is applicable only during the sector erase operation and will be ignored if written during the chip erase or programming operation. the erase suspend command (b0h) will be allowed only during the sector erase operation that will include the sector erase time-out period after the sector erase commands (30h). writing this command during the time-out will result in immediate termination of the time-out period and suspension of the erase operation. any other command written during the erase sus- pend mode will be ignored except the erase resume command. writing the erase resume command re- sumes the erase operation. the addresses are ?on?-cares when writing the erase suspend or erase resume command. when the erase suspend command is written during the sector erase operation, the device will take a max- imum of 15 m s to suspend the erase operation. when the device has entered the erase-suspended mode, the ry/by output pin and the d7 bit will be at logic ?? and d6 will stop toggling. the user must use the address of the erasing sector for reading d6 and d7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause d2 to toggle. (see the section on d2). after entering the erase-suspend-read mode, the user can program the device by writing the appropriate com- mand sequence for byte program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular byte program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-program mode will cause d2 to toggle. the end of the erase-suspended program operation is detected by the ry/by output pin, data polling of d7, or by the toggle bit 1 (d6) which is the same as the reg- ular byte program operation. note that d7 must be read from the byte program address while d6 can be read from any address. every time a sector erase suspend command followed by an erase resume command is written, the internal (pulse) counters are reset. these counters are used to count the number of high voltage pulses the memory cell requires to program or erase. if the count exceeds a certain limit, then the d5 bit will be set (exceeded time limit ?g). this resetting of the counters is nec- essary since the erase suspend command can poten- tially interrupt or disrupt the high voltage pulses. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. an- other sector erase suspend command can be written after the chip has resumed erasing. reset hardware reset the d-series card may be reset by driving the reset pin to v il . the reset pin must be kept low (v il ) for at least 500 ns. any operation in progress will be terminated and the internal state machine will be reset to the read mode 20 m s after the reset pin is driven low. if a hardware reset occurs during a pro- gram operation, the data at that particular location will be indeterminate. when the reset pin is low and the internal reset is complete, the card goes to standby mode and cannot be accessed. also, note that all the data output pins are tri-stated for the duration of the reset pulse. once the reset pin is taken high, the card requires 500 ns of wake up time until outputs are valid for read access. mode d7 d6 d2 program d7 toggles 1 erase 0 toggles toggles erase suspend read (note 1) (erase-suspended sector) 1 1 toggles erase suspend program d7 (note 2) toggles 1 (note 2)
18 amc0xxdflka write operation status table 8. write operation status notes: 1. performing successive read operations from the erase-suspended sector will cause d2 to toggle. 2. performing successive read operations from any address will cause d6 to toggle. 3. reading the byte address being programmed while in the erase-suspend program mode will indicate logic ? at the d2 bit. however, successive reads from the erase-suspended sector will cause d2 to toggle. status d7 d6 d5 d3 d2 in progress byte program in embedded program algorithm d7 toggle 0 0 1 embedded erase algorithm 0 toggle 0 1 toggle erase suspended mode erase suspend read (erase suspended sector) 1100 toggle (note 1) erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) d7 toggle (note 2) 01 1 (note 3) exceeded time limits byte program in embedded program algorithm d7 toggle 1 0 1 program/erase in embedded erase algorithm 0 toggle 1 1 n/a erase suspended mode erase suspend program (non-erase suspended sector) d7 toggle 1 1 n/a
amc0xxdflka 19 start fail no d7 = data? no pass ye s no ye s d7 = data? d5 = 1? ye s read byte (d0?7) addr = va read byte (d0?7) addr = va 19521d-4 note: d7 is rechecked even if d5 = 1 because d7 may change simultaneously with d5. figure 3. data polling algorithm va = valid address va = byte addr for write operation va = any segment (sector) address during segment (sector) erase operation
20 amc0xxdflka start fail ye s d6 = toggle? ye s pass no no ye s d6 = toggle? d5 = 1? no read byte (d0?7) addr = va read byte (d0?7) addr = va 19521d-5 note: d6 is rechecked even if d5 = 1 because d6 may stop toggling at the same time as d5 changes to ?? figure 4. toggle bit 1 algorithm
amc0xxdflka 21 19521d-6 * d7 = valid data (the device has completed the embedded operation.) figure 5. ac waveforms for data polling during embedded algorithm operations d0?6 valid data t oe d7 = valid data high-z ce oe we d7 d 7 d0?6 d0?6 = invalid * t oeh t ce t ch t df t oh t whwh 3 or 4 19521d-7 * d6 stops toggling (the device has completed the embedded operation.) figure 6. ac waveforms for toggle bit 1 during embedded algorithm operations ce t oeh we oe d6 = stop toggling d0?7 valid d6 = toggle d6 = toggle data (d0?7) * t oe
22 amc0xxdflka embedded algorithms 19521d-8 figure 7. byte-wide programming and erasure overview software polling from memory segment write embedded programming or erase command sequence to memory segments completed the embedded algorithm operations completely automate the programming and erase procedure by internally exe- cuting the algorithmic command sequence of original amd devices. the devices automatically provide write opera- tion status information with standard read operations. see table 3 or 4 for program command sequence. start
amc0xxdflka 23 embedded algorithms 19521d-9 figure 8. byte-wide programming flow chart activity initialize programming variables: ef = error flag ef = 0 = no programming error ef = 1 = programming error pgm = embedded byte write command sequence cycle #1? (table 3 or 4) adrs = appropriate address for memory segment vdat = valid data pd = program data fmd = flash memory data program complete initialization: ef = 0 read adrs/fmd program error begin programming write pgm get adrs/pd vdat = pd write adrs/pgm write adrs/vdat no ye s ye s ye s no fmd = vdat no fmd = vdat more data begin software polling subroutine (figure 9)
24 amc0xxdflka embedded algorithms d5 = 1? 19521d-10 note: d7 is checked even if d5 = 1 because d7 may have changed simultaneously with d5 or immediately after d5. figure 9. byte-wide software polling for programming subroutine va = byte address for programming no = program time not exceeded limit yes = program time exceed limit, device failed ef = error flag start subroutine no ye s ye s ye s no d7 = data? no d7 = data subroutine return recommend 8 m s time out from previous data polling device failed to program ef = 1 device passed read byte (d0?7) addr = va read byte (d0?7) addr = va
amc0xxdflka 25 embedded algorithms 19521d-11 figure 10. byte-wide erasure flow chart activity ers = erase command sequence (even byte per table 3, odd byte per table 4) seg adrs = segment address = 0 ef = error flag = 0 fmd = flash memory data ffh = erased flash memory data erase complete erase error begin erase no ye s no ye s no fmd = ffh ye s fmd = ffh last segment address initialization: ef = 0 seg adrs = 0 write ers cycle#1? write segadrs/ers cycle #6 read seg adrs/fmd begin software polling subroutine (figure 11) increment seg adrs
26 amc0xxdflka embedded algorithms d5 = 1? 19521d-12 figure 11. byte-wide software polling erase subroutine d7 = 1 yes = erase complete no = erase not complete d5 = 1 yes = erase time exceeded limit, device failed no = erase time has not exceeded limit x = don? care start subroutine no ye s ye s ye s no d7 = 1? no d7 = 1 subroutine return device failed to program ef = 2 device passed read byte (d0?7) addr = x read byte (d0?7) addr = x
amc0xxdflka 27 word-wide programming and erasing word-wide programming the word-wide programming sequence will be as usual per table 5. the program word command is a0a0h. each byte is independently programmed. for example, if the high byte of the word indicates the successful completion of programming via one of its write status bits such as d15, software polling should continue to monitor the low byte for write completion and data veri?ation, or vice versa. dur- ing the embedded programming operations the de- vice executes programming pulses in 8 m s increments. status reads provide information on the progress of the byte programming relative to the last complete write pulse. status information is automat- ically updated upon completion of each internal write pulse. status information does not change within the 8 m s write pulse width. word-wide sector erasing the word-wide erasing of a memory sector pair is sim- ilar to word-wide programming. the erase word com- mand is a 6 bus cycle command sequence per table 5. each byte is independently erased and veri?d. word-wide erasure reduces total erase time when compared to byte erasure. each flash memory device in the card may erase at different rates. therefore each device (byte) must be veri?d separately. 19521d-13 figure 12. embedded algorithm word-wide programming and erasure overview software polling from memory segments write embedded programming or erase command sequence to memory segments completed the embedded algorithm operations completely automate the parallel programming and erase procedures by inter- nally executing the algorithmic command sequences of amds flashrite and flasherase algorithms. the devices automatically provide write operation status information with standard read operations. see table 5 for program command sequence. start
28 amc0xxdflka embedded algorithms 19521d-14 figure 13. word-wide programming flow chart activity initialize programming variables: pgm =embedded word write command sequence cycle #1? (table 5) ef = error flag adrs = appropriate address for memory segment (cycle #4) pdw = program data word vwdat = valid word data ef = error flag ef = 0 = no failure ef = 1 = low byte program error ef = 2 = high byte program error ef = 3 = word-wide program error fmd = flash memory data program complete initialization: ef = 0 program error begin programming no ye s ye s ye s no fmd = vwdat no fmd = vwdat more data get adrs/pdw vwdat = pdw write pgm write adrs/pdw wait 8 m s read adrs/fmd begin software polling subroutine (figure 14)
amc0xxdflka 29 embedded algorithms 19521d-15 figure 14. word-wide software polling program subroutine va = word address for programming v data = valid data d5/13 = 1? yes = erase time has exceeded limit, device failed no = erase time has not exceeded limit begin subroutine ye s no d7 = v data ? ye s d15 = v data ? subroutine return low byte program time exceeded limit, ef = 1 read byte (d0?7) addr = va read byte (d8?15) addr = va no d5 = 1? read byte (d0?7) addr = va ye s no d7 = v data ? no no d13 = 1? read byte (d8?15) addr = va no d15 = v data ? ye s ye s high byte program time exceeded limit, ef = 2 + ef ye s
30 amc0xxdflka embedded algorithms 19521d-16 figure 15. word-wide erasure flow chart activity ers = segment erase command sequence (table 5) seg adrs = segment address ef = error flag ef = 0 = no failure ef = 1 = low byte erase error ef = 2 = high byte erase error ef = 3 = word-wide erase error fmd = flash memory data erase complete wait 2 seconds erase error begin erase no ye s ye s ye s no fmd = ffffh no fmd = ffffh last segment address read seg adrs/fmd begin software polling subroutine (figure 16) inc seg adrs write ers cycle #6: seg adrs initialization: ef = 0 seg adrs = 0 write ers cycle #1?
amc0xxdflka 31 embedded algorithms 19521d-17 figure 16. word-wide software polling erase subroutine d7/15 = 1 yes = erase complete no = erase not complete d5/13 = 1 yes = erase time has exceeded limit, device failed no = erase time has not exceeded limit begin subroutine ye s no d7 = 1? ye s d15 = 1? subroutine return low byte program time exceeded limit, ef = 1 read byte (d0?7) read byte (d8?15) no d5 = 1? read byte (d0?7) ye s no d7 = 1? no no d13 = 1? no d15 = 1? ye s high byte program time exceeded limit, ef = 2 + ef ye s read byte (d8?15) ye s
32 amc0xxdflka absolute maximum ratings storage temperature . . . . . . . . . . . . . ?0 c to +70 c ambient temperature with power applied. . . . . . . . . . . . . . . . . 0 c to +70 c voltage at all pins (note 1) . . . . . . . . ?.5 v to +7.0 v v cc (note 1). . . . . . . . . . . . . . . . . . . . ?.5 v to +6.0 v output short circuit current (note 2) . . . . . . . 40 ma notes: 1. minimum dc voltage on input or i/o pins is ?.5 v. during voltage transitions, inputs may overshoot v ss to ?.0 v for periods of up to 20 ns. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 2.0 v for periods up to 20ns. 2. no more than one output shorted at a time. durations of the short circuit should not be greater than one second. conditions equal v out = 0.5 v or 5.0 v, v cc = v cc max. these values are chosen to avoid test problems caused by tester ground degradation. this parameter is sampled and not 100% tested, but guaranteed by characterization. stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this speci?ation is not implied. exposure of the device to absolute maximum rating conditions for ex- tended periods may affect device reliability. operating ranges commercial (c) devices case temperature (t c ) . . . . . . . . . . . . . .0 c to +70 c v cc supply voltages . . . . . . . . . . . . +4.75 v to 5.25 v operating ranges de?e those limits between which the functionality of the device is guaranteed.
amc0xxdflka 33 dc characteristics byte-wide operation note: one flash device active, all the others in standby. parameter symbol parameter description test description min max unit i li input leakage current v cc = v cc max, v in = v cc or v ss for all cards: ce , reg , we , reset 4 mb + 20 m a 8 mb + 20 20 mb + 20 32 mb + 20 i lo output leakage current v cc = v cc max, v out = v cc or v ss 4 mb 20 m a 8 mb 20 20 mb 20 32 mb 20 i ccs v cc standby current (see note) v cc = v cc max ce = v cc 0.2 v v in = v cc or gnd 4 mb 1.7 ma 8 mb 1.7 20 mb 1.7 32 mb 1.7 i cc1 v cc active read current (see note) v cc = v cc max, ce = v il , oe = v ih , i out = 0 ma, at 3.3 mhz 45 ma i cc2 v cc write/erase current (see note) ce = v il programming in progress 65 ma v il input low voltage ?.5 0.8 v v ih input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 3.2 ma, v cc = v cc min 0.40 v v oh output high voltage i oh = 2.0 ma, v cc = v cc min 3.8 v cc v v lko low v cc lock-out voltage 3.2 4.2 v
34 amc0xxdflka word-wide operation note: two flash devices active, all the others in standby. parameter symbol parameter description test description min max unit i li input leakage current v cc = v cc max, v in = v cc or v ss for all cards: ce , reg , we , reset 4 mb +20 m a 8 mb +20 20 mb +20 32 mb +20 i lo output leakage current v cc = v cc max, v out = v cc or v ss 4 mb 20 m a 8 mb 20 20 mb 20 32 mb 20 i ccs v cc standby current (see note) v cc = v cc max ce = v cc 0.2 v v in = v cc or gnd 4 mb 1.7 ma 8 mb 1.7 20 mb 1.7 32 mb 1.7 i cc1 v cc active read current (see note) v cc = v cc max, ce = v il , oe = v ih , i out = 0 ma, at 3.3 mhz 45 ma i cc2 v cc programming current (see note) ce = v il programming in progress 65 ma v il input low voltage ?.3 0.8 v v ih input high voltage 0.7v cc v cc + 0.3 v v ol output low voltage i ol = 3.2 ma, v cc = v cc min 0.40 v v oh output high voltage i oh = 2.0 ma, v cc = v cc min 3.8 v cc v v lko low v cc lock-out voltage 3.2 4.2 v
amc0xxdflka 35 pin capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25 c, f = 1.0 mhz. switching ac characteristics read only operation (note 1) note: 1. input rise and fall times (10% to 90%): 10 ns, input pulse levels: v ol and v oh , timing measurement reference level: inputs: v il and v ih outputs: v il and v ih parameter symbol parameter description test conditions max unit c in1 all except a1?9 v in = 0 v 2 pf c out output capacitance v out = 0 v 2 pf c in2 a1?9 v in = 0 v 2 pf c i/o i/o capacitance d0?15 v i/o = 0 v 2 pf card speed parameter symbol parameter description -150 ns unit jedec standard min max t avav t rc read cycle time 150 ns t elqv t ce chip enable access time 150 ns t avqv t acc address access time 150 ns t glqv t oe output enable access time 75 ns t elqx t lz chip enable to output in low-z 5 ns t ehqz t df chip disable to output in high-z 75 ns t glqx t olz output enable to output in low-z 5 ns t ghqz t df output disable to output in high-z 75 ns t axqx t oh output hold from first of address, ce , or oe change 5 ns
36 amc0xxdflka ac characteristics write/erase/program operations notes: 1. rise/fall 10 ns. 2. maximum speci?ation not needed due to the devices internal stop timer that will stop any erase or write operation that exceed the device speci?ation. 3. embedded program operation of 8 m s consist of 6 m s program pulse and 2 m s write recovery before read. this is the minimum time for one pass through the programming algorithm. d5 = ? only after a byte takes longer than 2 ms to write. card speed parameter symbol parameter description -150 ns unit jedec standard min typ max t avav t wc write cycle time 150 ns t avwl t as address setup time 20 ns t wlax t ah address hold time 20 ns t dvwh t ds data setup time 50 ns t whdx t dh data hold time 20 ns t oeh output enable hold time for embedded algorithm 0 ns t whgl t wr write recovery time before read 6 m s t ghwl read recovery time before write 20 m s t elwl t cs ce setup time 0 ns t wheh t ch ce hold time 20 ns t wlwh t wp write pulse width 45 ns t whwl t wph write pulse width high 50 ns t whwh3 embedded programming operation (notes 1, 2, 3) 8 m s 2ms t whwh4 embedded erase operation for each 64k byte memory sector (notes 1, 2) 15 s t vcs v cc setup time to ce low 50 m s
amc0xxdflka 37 key to switching waveforms switching waveforms must be steady may change from h to l may change from l to h does not apply don? care, any change permitted will be steady will be changing from h to l will be changing from l to h changing, state unknown center line is high- impedance ?ff state waveform inputs outputs ks000010 19521d-18 note: ce refers to ce 1 and ce 2. figure 17. ac waveforms for read operations addresses ce oe we outputs addresses stable high-z high-z (t df ) (t oh ) output valid t acc t oe (t ce ) t rc t oe
38 amc0xxdflka switching waveforms 19521d-19 note: sa is the sector address for sector erase per table 6. figure 18. ac waveforms segment/sector byte erase operations t as t wp t cs t dh xxxxh xxxxh sa ce oe we data v cc aah 55h addresses xxxxh t vcs t ds xxxxh xxxxh t wph t ghwl t ah aah 55h 80h 10h/30h t wp
amc0xxdflka 39 switching waveforms v cc t vcs 19521d-20 notes: 1. figure indicates last two bus cycles of four bus cycle sequence. 2. pa is address of the memory location to be programmed. 3. pd is data to be programmed at byte address. 4. d 7 is the output of the complement of the data written to the device. 5. d out is the output of the data written to the device. figure 19. ac waveforms for byte write operations d out pd t ah data polling t df t oh t oe t ds t cs t wph t dh t wp t ghwl addresses ce oe we data d 7 xxxxh pa a0h pa t wc t rc t as t whwh3 t ce
40 amc0xxdflka ac characteristics?lternate ce controlled writes write/erase/program operations notes: 1. rise/fall 10 ns. 2. maximum speci?ation not needed due to the internal stop timer that will stop any erase or write operation that exceed the device speci?ation. 3. card enable controlled programming: flash programming is controlled by the valid combination of the card enable (ce 1, ce 2) and write enable (we ) signals. for systems that use the card enable signal(s) to de?e the write pulse width, all setup, hold, and inactive write enable timing should be measured relative to the card enable signal(s). 4. embedded program operation of 8 m s consist of 6 m s program pulse and 2 m s write recovery before read. this is the minimum time for one pass through the programming algorithm. d5 = ? only after a byte takes longer than 2 ms to write. card speed parameter symbol parameter description -150 ns unit jedec standard min max t avav t wc write cycle time 150 ns t avel t as address setup time 20 ns t elax t ah address hold time 55 ns t dveh t ds data setup time 50 ns t ehdx t dh data hold time 20 ns t gldv t oe output enable hold time for embedded algorithm 20 ns t ghel read recovery time before write 20 ns t wlel t ws we setup time before ce 0ns t ehwh t wh we hold time 0 ns t eleh t cp ce pulse width 80 ns t ehel t cph ce pulse width high (note 3) 50 ns t eheh3 embedded programming operation (notes 3, 4) 8 m s 2ms t eheh4 embedded erase operation for each 64k byte memory sector (notes 1, 2) s t vcs v cc setup time to write enable low 50 ms
amc0xxdflka 41 switching waveforms 19521d-21 notes: 1. figure indicates last two bus cycles of four bus cycle sequence. 2. pa is address of the memory location to be programmed. 3. pd is data to be programmed at byte address. 4. d 7 is the output of the complement of the data written to the device. 5. d out is the output of the data written to the device. figure 20. alternate ce controlled byte write operation timings d out pd t ah data polling t ds t ws t cph t dh t cp t ghel addresses we oe ce data v cc d 7 xxxxh pa a0h pa t wc t as t whwh3 or 4 t wh t vcs ce we ry/by t busy entire programming or erase operations the rising edge of the last we signal 19521d-22 figure 21. ry/by timing diagram during program/erase operations
42 amc0xxdflka reset t ready t rp ry/by 19521d-23 figure 22. reset timing diagram toggle d2 and d6 with oe we d6 d2 erase suspend enter embedded erasing erase resume enter erase suspend program erase erase suspend read erase suspend read erase suspend program erase erase complete 19521d-24 note: d2 is read from the erase suspended sector. figure 23. d2 vs. d6
amc0xxdflka 43 card information structure the d-series card contains a separate eeprom memory for the card information structure (cis). this allows all of the flash memory to be used for the common memory space. part of the common memory space could also be used to sore the cis. the eeprom used in the d-series card is designed to operate from a 5 v single power supply. table 9 shows the cis information stored in the amd flash memory card. system design and interface information power up and power down protection amds flash memory devices are designed to protect against accidental programming or erasure caused by spurious system signals that might exist during power transitions. the amd pc card will power-up into a read mode when v cc is greater than v lko of 3.2 v. erasing of memory sectors or memory segments can be accomplished only by writing the proper erase com- mand to the card along with the proper chip enable, output enable and write enable control signals. hot in- sertion of pc cards is not permitted by the pcmcia standard. note: hot insertion is de?ed as the socket condition where the card is inserted or removed with any or all of the following conditions present: v cc = v cch , v pp =v pph , address and/or data lines are active. system power supply decoupling the amd flash memory card has a 0.1 m f decoupling capacitor between the v cc and the gnd pins. it is rec- ommended the system side also have a 4.7 m f capac- itor between the v cc and the gnd pins.
44 amc0xxdflka table 9. amds cis for d-series cards note: see pcmcia speci?ations for parsing and card size values. tuple address 2 mbyte card tuple value tuples and remarks 00h 01h cistpl_device [common memory] 02h 03h tpl_link 04h 53h flash device, card speed: 53h = 150 ns (52h for 200 ns) 06h 0eh card size: 0eh = 4 mb, 1eh = 8 mb, 4eh = 20 mb, 7eh = 32 mb (note 1) 08h ffh end of tuple 0ah 18h cistpl_jedec [common memory] 0ch 03h tpl_link 0eh 01h amd mfg id code 10h 3dh device id code: 3dh = 16 mbit device, am29f016c 12h ffh end of tuple 14h 1eh cistpl_devicegeo 16h 07h tpl_link no ffh terminator 18h 02h dgtpl_bus: bus width 1ah 11h dgtpl_ebs: 11h = 64k byte erase block size 1ch 01h dgtpl_rbs: read byte size 1eh 01h dgtpl_wbs: write byte size 20h 01h dgtpl_part: number of partition 22h 01h fl device interleave: no interleave 24h ffh end of tuple 26h 15h cistpl_vers1 28h 03h tpl_link 2ah 04h major version number 1 2ch 01h minor version for pcmcia std. 2.0 2eh ffh end of tuple 30h 17h cistpl_device_a [attribute memory] 32h 04h tpl_link 34h 47h eeprom with extended speed 36h 3ah extended speed = 250 ns 38h 00h device size = 1 unit of 512 byte 3ah ffh end of tuple 3ch 80h vendor-speci? tuple 3eh 05h tpl_link 40h 41h ? 42h 4dh ? 44h 44h ? 46h 00h end text 48h ffh end of tuple 4ah 81h vendor speci? tuples: 81h : xxh ascii characters : xxh : 6ah xxh ascii characters 6ch ffh cistpl_end
amc0xxdflka 45 physical dimensions type 1 pc card trademarks copyright ?1996 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are trademarks of advanced micro devices, inc. product names used in this publication are for identi?ation purposes only and may be trademarks of their respective companies. 10.0 min (mm) 10.0 min (mm) 85.6 0.2 mm 54.0 0.1 mm 3.3 0.1 mm 34 1 35 68 front side back side
46 amc0xxdflka revision summary for amc0xxdflka global added 32 mbyte card availability. deleted 200 ns speed option. block diagram updated schematic to show correct number of ?sh de- vices for 32 mbyte card. pin description a24-a0 should all be driven. memory card operations simpli?d description of erase operations. table 1, common memory bus operations simpli?d bus operation table. table 2, attribute memory bus operations simpli?d attribute memory bus operation table. a bsolute maximum ratings & operating ranges increased operating & maximum temperature range to +70 c dc characteristics revised v ih to 0.7 v cc ac characteristics removed 200 ns timing characteristics table 9, amd cis for d-series cards corrected cis values for card density

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